Mosfet logic inverter for integrated circuits

ABSTRACT

The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET&#39;&#39;s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.

United States Patent [191 Proebsting Nov. 27, 1973 MOSFET LOGIC INVERTERFOR INTEGRATED CIRCUITS [73] Assignee: Moskek Company, Carrolton, Tex.

[22] Filed: Nov. 29, 1971 21 Appl. No.: 202,953

[52] US. Cl 330/35, 307/205, 307/214, 307/215, 307/218, 307/304 [51]Int. Cl. H03f 3/16 [58] Field of Search 330/35; 307/205, 307/214, 215,217, 218, 304

[56] References Cited UNITED STATES PATENTS 3,436,621 4/1969 Crawford307/304 X o DD INPUT Q5 Primary Examiner-Roy Lake AssistantExaminer-James B. Mullins Attorney-D. Carl Richards et al.

[57] ABSTRACT The specification discloses a logic inverter comprised ofa depletion mode MOSFET used as a resistive load between a drain supplyvoltage and an output and one or more enhancement mode MOSFET'sconnected between output and source supply voltage. The source and gateof the depletion mode device are electrically common, and the gates ofthe enhancement mode devices form the logic inputs. The use of oneenhancement mode device provides a simple inverter, a plurality ofenhancement mode devices in parallel form a NOR gate, and a plurality ofenhancement mode devices in series form a NAND gate. Combination NOR andNAND GATES may also be formed. The basic inverter circuit is alsocombined with a push-pull output stage to provide increased speed ofoperation, particularly at higher drain supply voltages. Still anotherembodiment utilizes an enhancement mode transistor connected between thedepletion mode transistor and the output of the basic inverter stage toprovide a disable function in which output drain current is switched offunder all logic input conditions.

6 Claims, 10 Drawing Figures o DD PATENIEUNHVZWJ 3.775.693

SHEET 1 OF 2 INPUT FIG. 3

MOSFET LOGIC INVERTER FOR INTEGRATED CIRCUITS The present inventionrelates to logic switching circuitry which employs MOSFET devices, andin particular relates to an improved inverter stage for inverting logicgates in integrated circuits.

Digital data processing systems have been fabricated as large-scaleintegrated (LSI) circuits using metal-oxide-semiconductor field effecttransistor (MOSFET) technology for some time. This type of LS] devicehas, for various processing reasons, generally utilized p-channelenhancement mode devices, although n-channel enhancement modetransistors have certain inherent advantages.

One of the major disadvantages heretofore associated with MOSFETcircuits has been the relatively large number of supply voltages, andthe relatively high magnitude of the supply voltages required to operatethe circuit efficiently. The higher number of supply voltages increasesthe complexity of the external circuitry associated with the MOSintegrated chips, and also increases the number of pins required tointerface the integrated circuit package with the external circuitry.The higher voltage results in greater power dissipation and requireslarger geometries to provide the necessary voltage breakdowncharacteristics.

One of the fundamental circuits required in a MOS- FET integratedcircuit is a simple inverter in which a resistive type loadinterconnects the drain voltage to the inverter output and anenhancement mode transistor connects the output to the source voltage.When the enhancement mode transistor is switched off, the output is atthe drain voltage, which is typically referred to as the logic l level.When the enhancement mode transistor is switched on, the output ispulled down to a level near the source voltage, which is typicallyreferred to as the logic level. The logic 0" level depends on therelative resistance of the enhancement mode transistor to that of theresistive type load. Although the use of a simple resistor as the loadhas the advantage that one of the output levels is the drain supplyvoltage, the circuit is not practical in integrated circuit form becausea diffused region having a resistance sufficiently large to provide alow level of power dissipation occupies a prohibitively large area.

One substitute for a diffused load resistor is an enhancement modetransistor in which the gate is connected to the drain supply voltage.However, this circuit has the disadvantage that the logic l level of theoutput can reach a potential equal only to the drain voltage V less thethreshold voltage V of the load transistor, which is typically severalvolts. Another disadvantage is that the output current of the loaddevice decreases very rapidly as the magnitude of the voltage on theoutput, which is the source of the load transistor, increases.

These objections to the use of an enhancement mode transistor as a loadcan be remedied by applying a voltage V to the gate of the transistor ofgreater magnitude than the drain voltage, but this requires anadditional supply voltage. In addition, such a circuit exhibitsundesirable nonlinearity in the output current of the inverter stagebecuase as the output voltage approaches drain voltage, both the sourceto drain voltage and the source to gate voltage of the load transistordecrease.

The logic l level at the output of the inverter can be raised to Vwithout the use of a higher gate voltage V by means of a so-calledbootstrap inverter. However, the bootstrap circuits require additionaldevices and have other disadvantages.

Still another circuit which has been used is the complimentary inverterhaving an n-channel enhancement mode transistor connected to thenegative voltage supply and a p-channel enhancement mode transistorconnected to the positive voltage supply, with the common drains beingthe output. The gates of the transistors are connected together andreceive the input signal. When the input signal is negative, then-channel enhancement mode device is turned off, the p-channelenhancement mode device is turned on, and the output is at the level ofthe positive supply voltage. When the input signal is positive, then-channel device is on, the p-channel device is off, and the output isat the level of the negative supply voltage. Such a complementaryinverter provides good switching characteristics and requires only onesupply voltage. However, the use of both n-channel and p-channel devicesrequires an unusually large amount of area on an integrated circuitchip, and also requires several additional processing steps whichsignificantly increases the cost of the circuit.

The inverter circuit of the present invention is comprised of adepletion mode MOS transistor connecting the drain supply voltage V tothe output with the gate of the transistor being electrically commonwith the output. At least one enhancement mode MOS transistor having thesame type channel as the depletion mode device provides a pathconnecting the output to a source voltage supply V The gate or gates ofthe enhancement mode device forms the input for the inverter circuit.The inverter circuit is useful for both pchannel and n-channelintegrated circuits, and has the advantages of providing an output logicl level when the enhancement mode device is switched off that issubstantially equal to the drain supply voltage, thus requiring only onevoltage supply. Perhaps more importantly, the current through thedepletion mode device remains substantially constant as the outputvoltage transitions toward the drain supply voltage, thus providingsignificantly greater switching speeds. The depletion mode device canalso be made significantly smaller than an enhancement mode device usedfor the same purpose, particularly where additional switching speed isnot required.

In accordance with another aspect of the invention, the performance ofthe inverter circuit is enhanced by providing a push-pull output stagecomprised of a pair of transistors connected in series between the drainand source voltages. The transistor connected to the source voltage isan enhancement mode device, and the transistor connected to the drainvoltage is preferably a depletion mode device, but may also be anenhancement mode device. The output from the basic inverter stage iscoupled to the gate of the depletion mode device, and the gate of theenhancement mode device in the output stage is connected to the logicinput to the basic inverter stage. For a given power dissipation, theimproved circuit has increased switching performance, particularly athigher supply voltages. However, the increased switching performance isachieved at the expense of flexibility of circuit design and therequirement for additional area on the chip.

In accordance with another aspect of the invention, an additionalenhancement mode device may be connected between the depletion modetransistor used as the load and the output of the inverter stage toprovide an on-off switching capability for output current. As mentioned,NOR and NAND gates may also be formed by providing additionalenhancement mode devices between the output of the inverter stage andthe source voltage.

The basic circuit of the invention is also highly useful as a linearamplifier having unusually high gain.

The novel features believed characteristic of this invention are setforth in the appended claims. The invention itself, however, as well asother objects and advantages thereof, may best be understood byreference to the following detailed description of illustrativeembodiments, when read in conjunction with the accompanying drawings,wherein:

FIG. 1 is a schematic circuit diagram of an inverter switching circuitin accordance with the present invention;

FIGS. la and lb are schematic circuit diagrams of additional invertinglogic gates in accordance with the present invention;

FIG. 2 is a schematic circuit diagram of another inverter switchingcircuit in accordance with the present invention;

FIG. 3 is a graph of the voltage with respect to time at a number ofnodes within the circuit shown in FIG. 2 during switching transitions;

FIG. 4 is a schematic circuit diagram of yet another switching circuitin accordance with the present invention; and

FIGS. 5-8 are schematic diagrams illustrating a process for fabricatingthe circuits of the present invention as LS1 circuits.

All specific embodiments herein described in detail utilize field effecttransistors fabricated by diffusing spaced, p-type source and drainregions into an n-type substrate, forming an insulating gate such assilicon dioxide over the channel region between the source and drainregions, and then forming a conductive gate electrode over the channelregion. Such a device is inherently an enhancement mode p-channeltransistor. Assuming that the source region of such a device is at Vtypically ground potential, and that the drain region is biased to anegative voltage, the device will conduct whenever the gate to sourcevoltage V is more negative than the threshold voltage V of the device,where V is always a negative value. When the magnitude of V is less thanV no significant conduction will occur.

The circuits of the present invention also utilize pchannel, depletionmode MOS transistors which have the same configuration, but have ap-channel between the diffused regions produced by ion implantation, aswill hereafter be described in greater detail. As a result, thedepletion mode devices conduct whenever the gate to source voltage V ismore negative than the pinchoff voltage V of the device, where V isalways positive. in order to stop conduction, the gate voltage withrespect to the source voltage must be more positive than the pinch-offvoltage. Thus, if the gate is at the same potential as the source, thedevice nevertheless continues to conduct.

Although all circuits are herein described as using pchanneltransistors, it is to be understood that the present invention isequally applicable to n-channel transistors. The n-channel enhancementmode and depletion mode devices function in the same manner as pchannelenhancement and depletion mode devices, except that the polarity of thevoltages is reversed. Accordingly, as used herein, the term low voltagerefers to the source or substrate voltage which is shown as groundpotential, and the term high voltage refers to the drain voltage, whichis a negative voltage for pchannel devices, and a positive voltage forn-channel devices. In some instances it will also be convenient to referto the higher or drain voltage levels as logic 1 levels, which forp-channel devices would typically be from 5.0 volts to l7.0 volts, andfor n-channel devices would typically be +5.0 volts to +17 volts. and tothe source, substrate, ground or lower voltage levels as the logic 0"levels.

Referring now to the drawings, the basic inverter circuit of the presentinvention is shown in FIG. 1. Transistors Q1 and Q2 are connected inseries between a drain voltage V and a source voltage, indicated by theconventional symbol for ground potential. The substrate of theintegrated circuit is typically at ground potential. As mentioned, thedrain voltage V would typically be from -5.0 volts to l7.0 volts forp-channel devices. The source of transistor Q1 and the drain oftransistor 02 are typically a common diffused region which is the output10 for the circuit. Transistor O1 is a depletion mode device, asindicated by the symbol D and transistor O2 is an enhancement modedevice as indicated by the symbol 5" The source of the depletion deviceO1 is electrically common with the gate. The gate of the enhancementmode device Q2 forms the input 12 to the inverter stage. The output 10is typically coupled to drive another circuit formed on the chip andalways has some stray capacitance represented by the capacitor 14. Inmost instances, the output 10 will drive a circuit that is open to DC.current, although for some applications a resistive element may also bedriven in parallel to the stray capacitance 14. In rare instances, thecapacitance 14 may be purposely increased to achieve a desired functionwithin the circuit.

In operation, the depletion mode transistor 01 is always tumed on bygate to source voltage equal to the pinch-off voltage and, therefore, isoperating substantially in the constant current condition. When theinput 12 is at a logic 0" level, or any potential less than thethreshold voltage V transistor Q2 will be turned off and the output 10will be substantially at V assuming that only the capacitance 14 isconnected to the output. When the input 12 is at a logic 1" level, orany voltage level significantly exceeding the threshold voltage oftransistor Q2, transistor 02 conducts current in proportion to the term(V -V As a result, the voltage level on output 10 moves toward thesubstrate potential, the ultimate level being a function of theconductance of transistors 01 and Q2 under the particular operatingconditions.

Since the depletion transistor 01 is always turned on, even whentransistor O2 is turned off, the output 10 will go all the way to Vassuming that the output is an open circuit to direct current. Thisprovides a very strong logic l level for operating additional circuitrywithin the chip. In addition, it should be noted that the transistor Q1operates either in or near the constant current mode at all times. Sincethe source and gate of transistor Q1 are electrically common, the sametransistor is always turned on by the same voltage, the pinch-offvoltage, and the current through transistor Q1 remains substantiallyconstant until the output voltage approaches within one pinch-off of thedrain supply voltage. This results in a substantially linear switchingcurve, as represented by transition 36 in FIG. 3. Since the current flowdoes not decrease as the output approaches the logic l level, the outputcan be switched from a logic 0 level to a logic I level in asubstantially shorter period of time than an enhancement mode devicehaving its gate connected to the drain voltage V It will be evident tothose skilled in the art that the basic inverter circuit of FIG. 1 canbe used to form any inverting logic gate. For example, a NOR gate may beformed by connecting one or more enhancement mode transistors O2 inparallel between the output and the source voltage, as illustrated inFIG. 1a. A NAND gate may be formed by connecting one or more enhancementmode transistors Q2 in series between the output 10 and the sourcevoltage, as illustrated in FIG. lb. If desired, a combination NOR-NANDgate can be formed by combinations of these.

The performance of the basic inverter circuit of FIG. 1 can besignificantly enhanced, particularly when using higher drain voltages,by the circuit illustrated in FIG. 2. The circuit of FIG. 2 utilizes thebasic inverter stage comprised of the depletion mode transistor Q3 andthe enhancement mode transistor 05. Again, additional enhancement modetransistors can be connected in parallel or in series with transistor Q5to provide the desired logic gate functions. A second stage is formed bydepletion mode transistor 04 and enhancement mode transistor Q6.Although transistor 04 is preferably a depletion mode transistor, it canbe an enhancement mode transistor and still provide a significantimprovement in performance. The output of the basic inverter stage isconnected by line 26 to the gate of transistor 04. The stray capacitanceof the line 26, including the gate of transistor 04, is represented bycapacitance 24. The input 22 is connected by line 32 to the gate oftransistor Q6. The drain of transistor O4 is connected to the drainsupply voltage V the source of transistor 04 and the drain of transistor06 are common and form the output of the output stage, and the source oftransistors O6 is connected to the source supply voltage. The output 30of the push-pull stage is normally connected to a line having a straycapacitance 34 which is substantially greater than the capacitance 24.

When the input 22 is at a logic l level, transistors Q5 and Q6 areturned on, and transistor Q6 pulls the output 30 down to a logic 0 levelnear ground. Transistor Q5 also pulls the output 20 of the inputinverter stage down to a logic 0" level near ground. It should be notedthat the gates of transistors Q3 and Q4 are nevertheless biased only tothe pinch-off voltage levels, thus keeping the current through thesedevices substantially constant. When the input 22 goes to a logic 0level, transistors Q5 and Q6 turn off. When transistor 05 turns off, thecurrent through transistor Q3 drives the output 20 to the drain supplyvoltage at a substantially constant rate. At the same time, transistorQ4 begins to drive the output 30 toward the drain supply voltage.However, since the capacitance 24 will customarily be much smaller thanthe capacitance 34, the output 20 will go negative, still assumingp-channel devices, at a much faster rate, assuming the same currentlevels. For example, if the gate of transistor Q4 were tied to theoutput 30, the rate at which the capacitor 34 would be charged might berepresented by transition 18 in FIG. 3. The output 20 is represented bytransition 36. It will be noted that the gate to source biased voltageon transistor Q4 is the difference between the voltages on outputs 20and 30. As a result, transistor Q4 is turned on harder than it would beif its gate were connected to the output 30, and the additional currentresults in charging rate represented by transition 40.

When the input'22 transitions to a logic l level to turn transistors Q5and Q6 on, the smaller capacitance 24 is again discharged more rapidlyso that the output 20 moves toward the source voltage along thetransition line 42, which is at a substantially greater rate than therate at which current can be discharged from the larger capacitance 34.As a result, the gate of transistor Q4 is made more positive withrespect to the source, tending to reduce the current through tansistorQ4, and permit transistor Q6 to pull the output 30 down at a greaterrate, as represented by transistion 44, than would have been the caseusing the inverter of FIG. 1, the transition of which is represented at45. At any point in time during the transition, the positive bias fromgate to source of transistor Q4 is represented by the difference intransitions 42 and 44, as indicated at 46.

In order to more fully appreciate the difference in performance of thecircuit of FIG. 1 and the circuit of FIG. 2, consider the followingexamples. assume that the circuit of FIG. 1 is biased by a drain supplyvoltage V of 5.0 volts and the source supply voltage is ground. Assumethat the output 10 transistions begween a logic 0" level of-l .0 voltand a logic l level of -5.0 volts. Assume also that capacitance 14 is1.0 picofarad and that the geometry of transistor 01 is chosen toconduct l0 microamperes of current. Under these conditions, the powersupplied to the device is the product of the current and voltage, whichis 50 microwatts. The time required to charge the capacitance 14 from--l.0 to "5.0 volts is approximately equal to the product of thecapacitance and the voltage change of 4 volts, divided by the current,which is equal to 400 nanoseconds. In this computation, it will be notedthat the current through transistor O1 is assumed to be constant.

Now assume that the circuit of FIG. 2 is also biased by a drain supplyvoltage V of 5.0 volts, and the source supply voltage is ground, andthat the output 30 swings from a logic "0" level ofl .0 volt to a logic1 level of -5.0 volts. Assume that transistors Q3 and Q4 are half thesize of transistor Q1 so that the current through each of thetransistors is 5.0 microamps, thus giving the same total powerconsumption of 50 microwatts as the circuit of FIG. 1. Assume also thatthe capacitance 24 is 0.1 picofarads and that the capacitance 34 is 1.0picofarad, the same as capacitance 14. The time required for output 20to transition from the logic 0 level of--l .0 volt to a logic 1" levelof 5.0 volts is again the product of the voltage change and thecapacitance, divided by the current, which is nanoseconds. Thus, it willbe noted that output 20 at the first stage of the circuit of FIG. 2 goesto the logic l level in one-fifth the time required for output 10 of thecircuit of FIG. 1. Assume that the average gate to source voltage ontransistor Q4 during the transition period is one-half of the differencein the logic l and logic levels, i.e., 2.0 volts, which is a slightlybest-case assumption. Assume also that the pinch-off voltage oftransistors Q1 and O4 is 4.0 volts. Then the total turnon voltage fortransistor O1 is 4.0 volts as compared to 6.0 volts for transistor Q4.The current through transistor O4 is then proportional to the square of6.0 volts, or 36 units of current. This compares with a total turnonvoltage of only 4.0 volts for transistor Q1, which provides 16 units ofcurrent. However, since transistor O4 is only half the size oftransistor Q1, the net result of transistor 04 is to provide only 18units of current. Thus, for a 5.0 volt drain supply voltage V thecircuits of FIGS. 1 and 2 are quite similar in switching performance.However, consider the situation if the drain voltage V is l7.0 volts. Inthat case, the voltage tending to turn transistor Q1 on remains at 4.0volts, continuing to give 16 units of current. However, the voltagebiasing transistor O4 is now the 4.0 volt pinchoff voltage, plusone-half of the voltage swing from -l.0 volts to l7.0 volts, the logic1" level, giving a total bias of 12.0 volts. This results in 72 units ofcurrent through transistor Q4, considering the transitor O4 is half thesize of transitor Q1. As a result of the higher drain voltage, thecircuit of FIG. 2 will switch the output from the logic 0" to the logicl level in less than one-fourth the time required for circuit of FIG. 1when using the same higher drain voltage.

FIG. 4 illustrates another embodiment of the inverter circuit of thepresent invention. The circuit of FIG. 4 includes a depletion modetransistor Q7 and enhancement mode transistors Q8 and Q9. Thetransistors Q7 and Q8 function precisely as transistors Q1 and O2 in thecircuit of FIG. 1 as heretofore described. The transistor O9 isconnected between the source of the depletion mode transistor Q7 and theoutput node 50, and provides a means for disabling current from outputnode 50. Thus, in order to obtain a logic I level on the output 50, alogic l level must be applied to the gate 52 of transistor Q9 so thattransistor Q9 will be turned on. Of course, it will be appreciated thatadditional enhancement mode transistors can be connected either inseries or in parallel with transistor O9 in order to perform additionallogic gate functions, as heretofore described in FIGS. la and 1b.

Although the circuit of FIG. 1 is particularly useful in MOSFET digitalintegrated circuits, which are of primary commercial importance at thepresent time, the circuit configuration of FIG. 1 is also an amplifierof exceptionally high gain and quality when biased and operated with theoutput signal in the midrange between the drain voltage supply V and thesource voltage supply VSSI FIGS. -8 illustrate the steps of a double ionimplantation process which may be used to fabricate the circuitry of thepresent invention. FIG. 5 shows a portion of an n-type silicon substrate54 of a monolithic chip in which both enhancement mode and depletionmode pchannel FET devices are to be formed. A silicon dioxide layer 56is deposited on substrate 54 by conventional thermal growth techniquesand openings 58, 60, 62 and 64 made therethrough using conventionalphotoresist and selective etching techniques. P-type diffusions are thenmade through openings 58 and 62 to form p-type source regions 66 and 68,respectively, and through openings 60 and 64 to form p-type drainregions 70 and 72, respectively. Silicon dioxide layer 56 is thenstripped from substrate 54 and a new silicon dioxide layer, generallyindicated by numeral 74 and having thick regions 76 and thin regions 78and 80 is formed on substrate 54. Thin regions 78 and 80 are disposedabove the channel areas, between source and drain regions 66 and 70 andsource and drain regions 68 and 72, respectively, of the FET devices.The substrate 54 as illustrated in FIG. 6 is subjected to an ionimplantation process in which p-type dopants which have a preselectedenergy are implanted in the surface of substrate 54. The energy of theions is arranged to permit the dopants to penetrate the thin regions 78and 80, but is insufi'icient to permit the ions to penetrate thickregions 76. The dosage of the dopants thus implanted is controlled toreduce the threshold voltage of the FET devices being formed to a valuesuitable for enhancement mode devices.

After that ion implantation step, a thin shield 82 of metal or othermaterial is placed over thin portion 78 which is disposed above thechannel region of the device which is to be an enhancement mode device.Substrate 54 is then subjected to another ion implantation step andadditional ions are implanted below thin region 80 of layer 74. Thedosage of ions implanted is sufficient to convert the channel disposedbelow thin region 80 to a p-type layer, thereby providing a depletionmode device. The shield 82 is removed from thin portion 78 and openings84, 86, 88 and 90 cut through thick portions 76, over regions 66, 70, 68and 72, respectively. Finally, a metalized layer is deposited oversilicon dioxide layer 74 and patterned to form source contacts 92 and 94above regions 66 and 68, respectively, drain contacts 96 and 98 aboveregions 70 and 72, respectively, and the metalized gates 100 and 102above thin portions 78 and 80 of layer 74.

Although preferred embodiments of the invention have been described indetail, it is to be understood that various changes, substitutions, andalterations can be made therein without departing from the spirit andscope of the invention as defined by the appended claims.

What is claimed is:

1. The integrated circuit including the inverter gate comprising:

a depletion mode field effect transistor coupling a drain voltage to anoutput node, the gate of the depletion mode field effect transistorbeing connected to the output node,

at least one enhancement mode field effect transistor coupling theoutput node to a source voltage, the gate of the enhancement modetransistor being the input, and

at least one enhancement mode field effect transistor coupling thesource of the depletion mode field effect transistor to the output node,the gate of said last mentioned enhancement mode field effect transistorbeing a logic input for enabling the inverter gate.

2. The integrated circuit of claim 1 wherein all field effecttransistors are p-channel devices.

3. The integrated circuit of claim I wherein all field effecttransistors are n-channel devices.

4. The integrated circuit including the inverter circuit comprising:

a first depletion mode field effect transistor coupling a drain voltageto a first output node, the gate of coupling the second output node to asource voltage, the gate of the second enhancement mode field effecttransistor being connected to the gate of the first enhancement modefield effect transistor.

5. The integrated circuit of claim 4 wherein the field effecttransistors are p-channel devices.

6. The integrated circuit of claim 4 wherein the field effecttransistors are n-channel devices.

UNITED STATES PATENT AND TRADEMARK OFFICE CERTIFICATE OF CORRECTIONPATENT NO. 3,775,693

DATED 1 November 27, I973 INVENTOR(S) Robert J. Proebsting It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

In Claim 1, at:

Column 8, line 47, delete "to an output node"; Column 8, line 49, change"output node" to source; Column 8, line 51, change the first "the" toan.

Signed and Scaled this Twelfth Day Of vJ||II1979 [SEAL] Arrest:

RU C M ASON DONALD W. BANNER Arresting Ojficer Commissioner of Patentsand Trademarks

1. The integrated circuit including the inverter gate comprising: adepletion mode field effect transistor coupling a drain voltage to anoutput node, the gate of the depletion mode field effect transistorbeing connected to the output node, at least one enhancement mode fieldeffect transistor coupling the output node to a source voltage, the gateof the enhancement mode transistor being the input, and at least oneenhancement mode field effect transistor coupling the source of thedepletion mode field effect transistor to the output node, the gate ofsaid last mentioned enhancement mode field effect transistor being alogic input for enabling the inverter gate.
 2. The integrated circuit ofclaim 1 wherein all field effect transistors are p-channel devices. 3.The integrated circuit of claim 1 wherein all field effect transistorsare n-channel devices.
 4. The integrated circuit including the invertercircuit comprising: a first depletion mode field effect transistorcoupling a drain voltage to a first output node, the gate of the firstdepletion mode field effect transistor being connected to the firstoutput node, a first enhancement mode field effect transistor couplingthe first output node to a source voltage, the gate of the firstenhancement mode field effect transistor being connected to an inputterminal, a second depletion mode field effect transistor coupling adrain voltage to a second output node, the gate of the second depletionmode field effect transistor being connected to the first output node,and a second enhancement mode field effect transistor coupling thesecond output node to a source voltage, the gate of the secondenhancement mode field effect transistor being connected to the gate ofthe first enhancement mode field effect transistor.
 5. The integratedcircuit of claim 4 wherein the field effect transistors are p-channeldevices.
 6. The integrated circuit of claim 4 wherein the field effecttransistors are n-channel devices.